One of the more popular programs that I’ve written is this 6502 memory test. One person using this test to checkout his Mimeo, recently discovered that it doesn’t work with his early white 6502. Turns out that that particular 6502 is a nice collectors piece, without a functioning ROR instruction. I used the ROR instruction at the end of the third test, so the program hangs when run on an early 6502 with the missing ROR functionality.

;
;
; all test 2 passes complete – prepase for test 3
;
LDA #$7F
BNE NX_TEST ;always branch

CHK_TEST3 ;floating zeros in progress or done
CPY #3
BNE CHK_TEST4
;
; pass of test 3 complete – 8 passes in all with 0 in each bit position
;
SEC
ROR TEST_PATRN ; rotate right – Carry to MSB, LSB to Carry
BCS NX_PASS2 ; keep going until zero bit reaches carry

I haven’t checked it, but I think the following code will accomplish the same basic test without using the ROR instruction.

;
;
; all test 2 passes complete – prepase for test 3
;
LDA #$FE
BNE NX_TEST ;always branch

CHK_TEST3 ;floating zeros in progress or done
CPY #3
BNE CHK_TEST4
;
; pass of test 3 complete – 8 passes in all with 0 in each bit position
;
SEC
ROL TEST_PATRN ; rotate left – MSB TO Carry, LSB = Carry
BCS NX_PASS2 ; keep going until zero bit reaches carry

I recently discovered that my 6502 cheat sheet has an egregious error. The ROL and ROR instructions move the Carry bit into the LSB and MSB (respectively), not the MSB and LSB. In other words the instructions are rotate through carry instructions.

I’m not sure how I managed to mess this one up or why it took so long for me to notice this or why no one else noticed it. Perhaps the functionality of these instructions are so well known that most people don’t need to refer to a cheat sheet to understand functionality. Clearly, I knew how they worked (or were supposed to work in the case of the early chips) when I wrote the 6502 memory test.