1101 SRAM Tester
From
The 1101 SRAM tester is a quick and dirty hack I did to enable testing of a fairly large batch of 1978 vintage MM1101 256x1 bit SRAMs that I bought for the upcoming SCELBI 8H project. I bought these parts ahead of time because I found a good deal on a fairly large quantity. I will not be able to run them in a real SCELBI system for a few months. Since they were so old, I figured that it would be wise to do some testing, in case a large percentage of the batch turned out to be bad. I know if I waited for the SCEBLI to come in I would not have a chance to return them. Also the SCELBI did not use sockets - all ICs are directly soldered to the boards, so testing before installing may save time down the road.
In the future I may modify the basic design to test 1Kx1 2102s for the SCELBI 8B. I haven't decided if I'm going to move the design perminately onto a SUPERPROTO board or not. It would be a fairly similar task to test 74 series TTL logic chips. However you may be able to find off the shelf testers for those chips, without too much trouble.
Here is my set up. Rather than figure out how to shut power on and off to the chip, I decided I could power off the entire Apple II when changing RAM chips. To start the test, you power on, and type Slot# CONTROL-P. If you have autostart ROMs in the Apple, the program will start automatically when you power on.
Here are the schematics. I did add .1UF caps between -12V and ground and -9V and ground, which I forgot to add to the schematics.
The program contains 4 tests. The floating ones and zeros test verify that each bit can be individually addressed with the chip.
- write all ones and read back all ones
- write all zero and read back all zeros
- floating zeros - writes all ones - then sets first bit to zero and verifies all bits are zero, except the first. Then sets first bit to one and resets second bit to zero. Then confirms all bits are one, except the second bit - repeats until all 256 bits are tested
- floating ones - same as floating zeros, except inverse
Here is the program: Load it the same way that you would load the SUPERPROTO diag image.
------- FILE sramtest_01.asm LEVEL 1 PASS 2
1 c96b PROCESSOR 6502
2 c96b ???? LIST ON
3 c96b ???? ;-------------------------------------------------------------------------
4 c96b ???? ; Defines - this code can be built one of four ways
5 c96b ???? ; 1. to run in RAM
6 c96b ???? ; 2. to run out of Hobbycard EEPROM
7 c96b ???? ;
8 c96b ???? ; select one of these three options
9 c96b ???? ;-------------------------------------------------------------------------
10 c96b ????
11 c96b ???? ;-------------------------------------------------------------------------
12 c96b ???? ; Constants
13 c96b ???? ;-------------------------------------------------------------------------
14 c96b ????
15 c96b ???? 00 df BS EQU $DF ;Backspace key, arrow left key
16 c96b ???? 00 8d CR EQU $8D ;Carriage Return
17 c96b ???? 00 9b ESC EQU $9B ;ESC key
18 c96b ???? 00 5c PROMPT EQU "\" ;Prompt character
19 c96b ????
20 c96b ???? ;-------------------------------------------------------------------------
21 c96b ???? ; MONITOR FUNCTIONS
22 c96b ???? ;-------------------------------------------------------------------------
23 c96b ????
24 c96b ???? fd ed COUT EQU $FDED ;Backspace key, arrow left key
25 c96b ???? ff 4a IOSAVE EQU $FF4A ;Save all registers
26 c96b ???? ff 3f IOREST EQU $FF3F ;Restore all registers
27 c96b ???? fc 58 HOME EQU $FC58 ;Clear Screen
28 c96b ???? fe 2c MOVE EQU $FE2C ;Move memory
29 c96b ???? ff 65 MON EQU $FF65 ;Monitor entry point
30 c96b ???? fe 89 SETKBD EQU $FE89 ;IN#0 sets default input vector
31 c96b ???? fe 93 SETVID EQU $FE93 ;PR#0 sets default output vector
32 c96b ???? fc a8 WAIT EQU $FCA8 ;wait function
33 c96b ???? fd da PRBYTE EQU $FDDA ;print hex byte
34 c96b ???? fc b4 NXTA4 EQU $FCB4 ;inc A4 and A1 until A1 = A2
35 c96b ????
36 c96b ????
37 c96b ???? ;-------------------------------------------------------------------------
38 c96b ???? ; I/O FUNCTIONS
39 c96b ???? ;-------------------------------------------------------------------------
40 c96b ???? c0 00 KEYBOARD EQU $C000 ;keyboard data
41 c96b ???? c0 10 KEYSTROBE EQU $C010 ;clears keyboard data
42 c96b ????
43 c96b ???? ;-------------------------------------------------------------------------
44 c96b ???? ; 6522A FUNCTIONS
45 c96b ???? ;-------------------------------------------------------------------------
46 c96b ???? c0 88 TMR2L EQU $c088 ;timer2 low byte
47 c96b ???? ; write: load LS byte
48 c96b ???? ;
49 c96b ???? ; read: to read low counter and clear interrupt
50 c96b ???? c0 89 TMR2H EQU $c089 ;timer2 high byte
51 c96b ???? ; wrt: high byte, transfer high and low to counter & enable int
52 c96b ???? ; rd: read high counter
53 c96b ???? ;
54 c96b ???? c0 8b ACR EQU $c08B ;aux control register
55 c96b ???? ;bit 5 = 0 timer 2 one shot mode
56 c96b ???? ;bit5 = 1 timer 2 count pulses output on PB 6
57 c96b ???? ;
58 c96b ???? c0 8c IFR EQU $c08C ;interrupt flag register
59 c96b ???? ; read: bit 7 state of IRQ, bit 5 timer 2 interrupt pending
60 c96b ???? ; write: set bit to clear interrupt
61 c96b ???? ;
62 c96b ???? c0 8e IER EQU $c08E ;interrupt enable register
63 c96b ???? ;bit 7 = 1 to set
64 c96b ???? ;bit 7 = 0 to clear
65 c96b ???? ;bit 5 = timer 2
66 c96b ????
67 c96b ???? ;-------------------------------------------------------------------------
68 c96b ???? ; Memory declaration
69 c96b ???? ;-------------------------------------------------------------------------
70 c96b ????
71 c96b ???? 00 22 WINDOWTOP EQU $22 ;top edge of window
72 c96b ????
73 c96b ???? 00 24 HEX1L EQU $24 ;End address of dump block
74 c96b ???? 00 25 HEX1H EQU $25
75 c96b ???? 00 26 HEX2L EQU $26 ;Begin address of dump block
76 c96b ???? 00 27 HEX2H EQU $27
77 c96b ????
78 c96b ???? 00 28 SAVEINDEX EQU $28 ;Save index in input buffer
79 c96b ???? 00 29 LASTSTATE EQU $29 ;Last input state
80 c96b ????
81 c96b ????
82 c96b ???? ;unused by monitor or applesoft
83 c96b ???? ; address setup for move command
84 c96b ???? 00 1a AD1L EQU $1a
85 c96b ???? 00 1b AD1H EQU $1b
86 c96b ???? 00 1c AD2L EQU $1c
87 c96b ???? 00 1d AD2H EQU $1d
88 c96b ???? 00 1e AD4L EQU $1e
89 c96b ???? 00 1f AD4H EQU $1f
90 c96b ???? ;address holding locations for monitor move command
91 c96b ???? 00 3c A1L EQU $3c
92 c96b ???? 00 3d A1H EQU $3d
93 c96b ???? 00 3e A2L EQU $3e
94 c96b ???? 00 3f A2H EQU $3f
95 c96b ???? 00 42 A4L EQU $42
96 c96b ???? 00 43 A4H EQU $43
97 c96b ????
98 c96b ???? 02 00 IN EQU $0200 ;Input buffer
99 c96b ????
100 c96b ???? 08 00 WORKING EQU $0800 ;Working Memory
101 c96b ????
102 c96b ???? c0 20 FLIP EQU $C020 ;Output flip-flop
103 c96b ???? c0 60 TAPEIN EQU $C060 ;Tape input
104 c96b ???? c0 00 KBD EQU $C000 ;keyboard input
105 c96b ???? c0 10 KBDCR EQU $C010 ;keybaord strobe clear
106 c96b ????
107 c96b ????
108 c96b ???? ;---------------------------------------------------------------------------
109 c96b ???? ; build in ACI Driver
110 c96b ???? ;---------------------------------------------------------------------------
111 c96b ???? ;BLD4RAM EQU 0
112 c96b ???? - IFCONST BLD4RAM
113 c96b ???? - ORG $800 ; build for memory
114 c96b ???? ELSE
115 c700 ORG $c700 ; plug in hobbyboard
116 c700 ENDIF
117 c700
118 c700
119 c700
120 c700 START
121 c700 24 20 BIT $20 ; pretend this is Disk 2, so autostart will run it automatically
122 c702 24 00 BIT $00
123 c704 24 03 BIT $03
124 c706 24 3c BIT $3C
125 c708 ;------------------------------------------------------------------------
126 c708 ; make sure no other card has 2K block selected
127 c708 ;--------------------------------------------------------------------------
128 c708 ad ff cf LDA $CFFF ;
129 c70b
130 c70b ;------------------------------------------------------------------------
131 c70b ; now figure out our slot
132 c70b ;--------------------------------------------------------------------------
133 c70b 20 4a ff JSR IOSAVE ; save registers
134 c70e 78 SEI ; block interrupts
135 c70f 20 58 ff JSR $FF58 ; move current PC to stack
136 c712 ba TSX
137 c713 bd 00 01 LDA $0100,X ; fetch high address
138 c716 8d f8 07 STA $07F8 ; save currently active card
139 c719 29 07 AND #$07 ; mask off $CX to get slot #
140 c71b a8 TAY
141 c71c 0a ASL
142 c71d 0a ASL
143 c71e 0a ASL
144 c71f 0a ASL
145 c720 aa TAX ; can be used to access 6522 VIA at C0SX
146 c721 99 78 04 STA $478,y ;save in scratchpad register
147 c724 a9 00 LDA #0 ;initialize pass count
148 c726 99 f8 04 STA $4f8,y ;save in scratchpad register
149 c729 99 f8 06 STA $6f8,y ;save interrupt count
150 c72c ;
151 c72c ; restore normal COUT and CIN
152 c72c ;
153 c72c 20 89 fe JSR SETKBD
154 c72f 20 93 fe JSR SETVID
155 c732
156 c732 20 58 fc JSR HOME ;clear screen
157 c735
158 c735 ;
159 c735 ; print banner
160 c735 ;
161 c735 a9 c9 LDA #>BANNER
162 c737 85 3d STA A1H
163 c739 a9 04 LDA #<BANNER
164 c73b 85 3c STA A1L
165 c73d 20 f5 c8 JSR PRINTSTRING
166 c740
167 c740 a9 01 LDA #1 ; prevents banner from being scrolled off top
168 c742 85 22 STA WINDOWTOP
169 c744
170 c744 a9 c9 LDA #>TESTSTART
171 c746 85 3d STA A1H
172 c748 a9 2c LDA #<TESTSTART
173 c74a 85 3c STA A1L
174 c74c 20 f5 c8 JSR PRINTSTRING
175 c74f ;
176 c74f ; initialize 6522A ports
177 c74f ; port A - output - 8 bit SRAM address bus
178 c74f c0 81 PORTA EQU $C081 ; PORT A
179 c74f c0 83 PORTADIR EQU $C083 ; PORT A direction
180 c74f ;
181 c74f c0 80 PORTB EQU $C080 ; PORT B
182 c74f c0 82 PORTBDIR EQU $C082 ; PORT B direction
183 c74f
184 c74f ; port B - output - bit 0 = low read - high write
185 c74f 00 01 PORTB_RW EQU $01
186 c74f
187 c74f ; port B - output - bit 1 = chip select
188 c74f 00 02 PORTB_CS EQU $02
189 c74f
190 c74f ; port B - output - bit 2 = SRAM write data bit
191 c74f 00 04 PORTB_WD EQU $04
192 c74f
193 c74f
194 c74f ; port B - input - bit 6 = SRAM data out
195 c74f 00 40 PORTB_IRD EQU $40
196 c74f ; port B - input - bit 7 = inverted SRAM data out
197 c74f 00 80 PORTB_RD EQU $80
198 c74f
199 c74f
200 c74f ad f8 07 LDA $07F8 ; fetch currently active card
201 c752 29 07 AND #$07 ; mask off $CX to get slot #
202 c754 0a ASL
203 c755 0a ASL
204 c756 0a ASL
205 c757 0a ASL
206 c758 aa TAX ; can be used to access 6522 VIA at C0SX
207 c759
208 c759 ;set up address
209 c759 a9 00 LDA #$0
210 c75b 9d 81 c0 STA PORTA,X ; start with address "0"
211 c75e a9 ff LDA #$FF
212 c760 9d 83 c0 STA PORTADIR,X ; set port A for output (address)
213 c763 ; set up control
214 c763 a9 02 LDA #PORTB_CS ; dessert Chip select and put in read mode - write data 0
215 c765 9d 80 c0 STA PORTB,X ;
216 c768 a9 07 LDA #PORTB_CS | PORTB_RW | PORTB_CS | PORTB_WD
217 c76a 9d 82 c0 STA PORTBDIR,X ; set port B direction
218 c76d
219 c76d STRTTEST
220 c76d 20 28 c8 JSR SRAMTEST
221 c770 b0 2a BCS BADBIT ; error
222 c772
223 c772 ad 00 c0 LDA KEYBOARD ; check to see if keyboard input (stops test)
224 c775 30 38 BMI TESTEXIT ; yes clear strobe, print finished and back to monitor
225 c777
226 c777 ;
227 c777 ; finished pass, increment count and print banner
228 c777 ;
229 c777
230 c777 a9 c9 LDA #>PASSED
231 c779 85 3d STA A1H
232 c77b a9 3b LDA #<PASSED
233 c77d 85 3c STA A1L
234 c77f 20 f5 c8 JSR PRINTSTRING
235 c782 ad f8 07 LDA $07F8 ; save currently active card
236 c785 29 07 AND #$07 ; mask off $CX to get slot #
237 c787 a8 TAY
238 c788 b9 f8 04 LDA $4F8,Y ;fetch pass count
239 c78b aa TAX
240 c78c e8 INX ;increment count
241 c78d 8a TXA
242 c78e 99 f8 04 STA $4f8,Y ;save count
243 c791 20 da fd JSR PRBYTE ;print hex number
244 c794
245 c794 a9 8d LDA #$8d
246 c796 20 ed fd JSR COUT ;newline
247 c799 38 SEC
248 c79a b0 d1 BCS STRTTEST
249 c79c
250 c79c BADBIT
251 c79c 48 PHA
252 c79d a9 c9 LDA #>ERRORRED
253 c79f 85 3d STA A1H
254 c7a1 a9 63 LDA #<ERRORRED
255 c7a3 85 3c STA A1L
256 c7a5 20 f5 c8 JSR PRINTSTRING
257 c7a8
258 c7a8 68 PLA
259 c7a9 20 da fd JSR PRBYTE ;print hex number
260 c7ac
261 c7ac 38 SEC
262 c7ad b0 0e BCS RETURNMON
263 c7af
264 c7af TESTEXIT
265 c7af ad 10 c0 LDA KEYSTROBE ;clear keyboard strobe
266 c7b2
267 c7b2 a9 c9 LDA #>ABORTED
268 c7b4 85 3d STA A1H
269 c7b6 a9 43 LDA #<ABORTED
270 c7b8 85 3c STA A1L
271 c7ba 20 f5 c8 JSR PRINTSTRING
272 c7bd ;
273 c7bd ; return to monitor
274 c7bd ;
275 c7bd RETURNMON
276 c7bd a9 00 LDA #0 ; reset window top
277 c7bf 85 22 STA WINDOWTOP
278 c7c1
279 c7c1 4c 65 ff JMP MON
280 c7c4
281 c7c4
282 c7c4
283 c7c4 - IFCONST BLD4RAM
284 c7c4 - ORG $0900 ; build for memory
285 c7c4 ELSE
286 c800 ORG $C800 ; plug in hobbyboard:w
287 c800 ENDIF
288 c800 ;
289 c800 ; MOVE from A1 to A4 - until A1 = ending address in A2
290 c800 ;
291 c800 MOV
292 c800 a0 00 LDY #0 ; index = 0
293 c802 a5 1a LDA AD1L
294 c804 85 3c STA A1L
295 c806 a5 1b LDA AD1H
296 c808 85 3d STA A1H
297 c80a
298 c80a a5 1c LDA AD2L
299 c80c 85 3e STA A2L
300 c80e a5 1d LDA AD2H
301 c810 85 3f STA A2H
302 c812
303 c812 a5 1e LDA AD4L
304 c814 85 42 STA A4L
305 c816 a5 1f LDA AD4H
306 c818 85 43 STA A4H
307 c81a MOV2
308 c81a b1 3c LDA (A1L),Y ; MOVE A1[0x3C] TO A2[0x3E] TO
309 c81c 91 42 STA (A4L),Y ; A4[0x42]
310 c81e MOVEWAIT
311 c81e d1 42 CMP (A4L),Y ; for eeprom - wait till write takes
312 c820 d0 fc BNE MOVEWAIT ; MSB not correct until write is done
313 c822 20 b4 fc JSR NXTA4
314 c825 90 f3 BCC MOV2
315 c827 60 RTS
316 c828
317 c828 SRAMTEST
318 c828 ad f8 07 LDA $07F8 ; fetch currently active card
319 c82b 29 07 AND #$07 ; mask off $CX to get slot #
320 c82d 0a ASL
321 c82e 0a ASL
322 c82f 0a ASL
323 c830 0a ASL
324 c831 aa TAX ; can be used to access 6522 VIA at C0SX
325 c832 ;
326 c832 ; write zeros
327 c832 ;
328 c832 a0 00 LDY #0
329 c834 WRITENEXT0BIT
330 c834 18 CLC
331 c835 20 af c8 JSR WRITEBIT
332 c838 c8 INY
333 c839 d0 f9 BNE WRITENEXT0BIT
334 c83b
335 c83b ;
336 c83b ; read all locations looking for zero
337 c83b ;
338 c83b READNEXT0BIT
339 c83b 18 CLC
340 c83c 20 ce c8 JSR READBIT
341 c83f b0 6c BCS BRKTEST
342 c841 c8 INY
343 c842 d0 f7 BNE READNEXT0BIT
344 c844
345 c844 ;
346 c844 ; write all ones
347 c844 ;
348 c844 WRITENEXT1BIT
349 c844 38 SEC
350 c845 20 af c8 JSR WRITEBIT
351 c848 c8 INY
352 c849 d0 f9 BNE WRITENEXT1BIT
353 c84b
354 c84b ;
355 c84b ; read all locations looking for zero
356 c84b ;
357 c84b READNEXT1BIT
358 c84b 38 SEC
359 c84c 20 ce c8 JSR READBIT
360 c84f b0 5c BCS BRKTEST
361 c851 c8 INY
362 c852 d0 f7 BNE READNEXT1BIT
363 c854
364 c854
365 c854 ;
366 c854 ; write and verify floating ones
367 c854 ;
368 c854 ;
369 c854 ; first write all zeros
370 c854 ;
371 c854 WRITENEXT0S
372 c854 18 CLC
373 c855 20 af c8 JSR WRITEBIT
374 c858 c8 INY
375 c859 d0 f9 BNE WRITENEXT0S
376 c85b
377 c85b 84 1a STY AD1L ; start with bit zero
378 c85d ;
379 c85d ; now loop - writing single bit into each location and checking that only that one bit is set
380 c85d ;
381 c85d READNEXTFLOAT1BITINCBIT
382 c85d a4 1a LDY AD1L ; current bit being tested
383 c85f 38 SEC
384 c860 20 af c8 JSR WRITEBIT ; set single bit at location Y
385 c863 ;
386 c863 ; read all locations looking for zero - except location of interest
387 c863 ;
388 c863 a0 00 LDY #0
389 c865 READNEXTFLOAT1BIT
390 c865 ; is this the bit that should be 1
391 c865 c4 1a CPY AD1L ;current bit?
392 c867 d0 03 BNE READNEXTFLOAT1BITZERO ;nope, we should read zero
393 c869 38 SEC ; expect to see the floating one
394 c86a b0 01 BCS READNEXTFLOAT1BITONE
395 c86c READNEXTFLOAT1BITZERO
396 c86c 18 CLC
397 c86d READNEXTFLOAT1BITONE
398 c86d 20 ce c8 JSR READBIT
399 c870 b0 3b BCS BRKTEST
400 c872 c8 INY
401 c873 d0 f0 BNE READNEXTFLOAT1BIT
402 c875
403 c875 ;
404 c875 ; done checking bit, now advance to next bit
405 c875 ;
406 c875 a4 1a LDY AD1L
407 c877 18 CLC
408 c878 20 af c8 JSR WRITEBIT ; clear previous single bit at location Y
409 c87b
410 c87b e6 1a INC AD1L
411 c87d d0 de BNE READNEXTFLOAT1BITINCBIT
412 c87f
413 c87f
414 c87f
415 c87f ;
416 c87f ; write and verify floating zeros
417 c87f ;
418 c87f ;
419 c87f ; first write all ones
420 c87f ;
421 c87f a0 00 LDY #0
422 c881 WRITENEXT1S
423 c881 38 SEC
424 c882 20 af c8 JSR WRITEBIT
425 c885 c8 INY
426 c886 d0 f9 BNE WRITENEXT1S
427 c888
428 c888 84 1a STY AD1L ; start with bit zero
429 c88a ;
430 c88a ; now loop - writing single bit into each location and checking that only that one bit is clear
431 c88a ;
432 c88a READNEXTFLOAT0BITINCBIT
433 c88a a4 1a LDY AD1L ; current bit being tested
434 c88c 18 CLC
435 c88d 20 af c8 JSR WRITEBIT ; clear single bit at location Y
436 c890 ;
437 c890 ; read all locations looking for zero - except location of interest
438 c890 ;
439 c890 a0 00 LDY #0
440 c892 READNEXTFLOAT0BIT
441 c892 ; is this the bit that should be 0
442 c892 c4 1a CPY AD1L ;current bit?
443 c894 d0 03 BNE READNEXTFLOAT0BITONE ;nope, we should read one
444 c896 18 CLC ; expect to see the floating one
445 c897 90 01 BCC READNEXTFLOAT0BITZERO
446 c899 READNEXTFLOAT0BITONE
447 c899 38 SEC
448 c89a READNEXTFLOAT0BITZERO
449 c89a 20 ce c8 JSR READBIT
450 c89d b0 0e BCS BRKTEST
451 c89f c8 INY
452 c8a0 d0 f0 BNE READNEXTFLOAT0BIT
453 c8a2
454 c8a2 ;
455 c8a2 ; done checking bit, now advance to next bit
456 c8a2 ;
457 c8a2 a4 1a LDY AD1L
458 c8a4 38 SEC
459 c8a5 20 af c8 JSR WRITEBIT ; set previous single bit at location Y
460 c8a8
461 c8a8 e6 1a INC AD1L
462 c8aa d0 de BNE READNEXTFLOAT0BITINCBIT
463 c8ac 18 CLC
464 c8ad
465 c8ad BRKTEST
466 c8ad 98 TYA
467 c8ae 60 RTS
468 c8af
469 c8af ;
470 c8af ; A = address, Carry set for 1, Carry not set for zero
471 c8af ;
472 c8af WRITEBIT
473 c8af 98 TYA
474 c8b0 9d 81 c0 STA PORTA,X ; set address
475 c8b3 b0 04 BCS WRITEBIT1
476 c8b5
477 c8b5 WRITEBIT0
478 c8b5 a9 03 LDA #PORTB_RW | PORTB_CS
479 c8b7 90 02 BCC WRITEBITCONT
480 c8b9
481 c8b9 WRITEBIT1
482 c8b9 a9 07 LDA #PORTB_RW | PORTB_WD | PORTB_CS
483 c8bb
484 c8bb WRITEBITCONT
485 c8bb 9d 80 c0 STA PORTB,X ; set to write and data bit
486 c8be
487 c8be 29 fd AND #<~PORTB_CS
488 c8c0 9d 80 c0 STA PORTB,X ; add CS - starts write
489 c8c3
490 c8c3 09 02 ORA #PORTB_CS
491 c8c5 9d 80 c0 STA PORTB,X ; remove CS - ends write
492 c8c8
493 c8c8 29 fe AND #<~PORTB_RW
494 c8ca 9d 80 c0 STA PORTB,X ; remove write
495 c8cd
496 c8cd 60 RTS
497 c8ce ;
498 c8ce ; input: A = address, carry set if expect a 1, otherwise a 0
499 c8ce ; output: carry set if error
500 c8ce ;
501 c8ce READBIT
502 c8ce 98 TYA
503 c8cf 9d 81 c0 STA PORTA,X ; set address
504 c8d2
505 c8d2 a9 02 LDA #PORTB_CS
506 c8d4 9d 80 c0 STA PORTB,X ; set read
507 c8d7
508 c8d7 29 fd AND #<~PORTB_CS
509 c8d9 9d 80 c0 STA PORTB,X ; low CS - starts read
510 c8dc
511 c8dc
512 c8dc bd 80 c0 LDA PORTB,X ; read data and inverted data (bits 6 and 7)
513 c8df 29 c0 AND #PORTB_RD | #PORTB_IRD ; keep data bits
514 c8e1
515 c8e1 90 07 BCC READBIT0 ; carry coming in is clear, expect 0 bit
516 c8e3
517 c8e3 c9 80 CMP #$80 ; compare to a 1 bit
518 c8e5 f0 07 BEQ READBITNOERR ; equal - no error
519 c8e7
520 c8e7 READBITERR
521 c8e7 38 SEC ; error indication
522 c8e8 b0 05 BCS READBITDONE ; always branch
523 c8ea
524 c8ea READBIT0 ; default - no error
525 c8ea c9 40 CMP #$40 ;expect a 0 bit
526 c8ec d0 f9 BNE READBITERR
527 c8ee
528 c8ee READBITNOERR
529 c8ee 18 CLC ;equal - no error
530 c8ef
531 c8ef READBITDONE
532 c8ef a9 02 LDA #PORTB_CS ; dessert Chip select and put in read mode - write data 0
533 c8f1 9d 80 c0 STA PORTB,X ;
534 c8f4
535 c8f4 60 RTS
536 c8f5
537 c8f5
538 c8f5
539 c8f5 PRINTSTRING
540 c8f5 a0 00 LDY #0
541 c8f7 PS1
542 c8f7 b1 3c LDA (A1L),Y
543 c8f9 f0 08 BEQ PSDONE
544 c8fb 09 80 ORA #$80
545 c8fd 20 ed fd JSR COUT
546 c900 c8 INY
547 c901 d0 f4 BNE PS1
548 c903 PSDONE
549 c903 60 RTS
550 c904
551 c904
552 c904
553 c904 31 31 30 31*BANNER DC "1101 TEST COPYRIGHT 2012 MIKE WILLEGAL",$0d,0
554 c92c 53 54 41 52*TESTSTART DC "STARTING TEST",$0d,0
555 c93b 50 41 53 53*PASSED DC "PASS: ",0
556 c943 54 45 53 54*ABORTED DC "TEST STOPPED BY KEYBOARD INPUT",$0d,0
557 c963 45 52 52 4f*ERRORRED DC "ERROR: ",0
558 c96b
559 c96b
